The present embodiments relate to semiconductor transistor fabrication and are more particularly directed to complementary transistors.
Integrated circuit technology continues to advance at a rapid pace, with many circuit technologies being implemented using semiconductor fabrication processes. With the advancement of semiconductor circuit fabrication, consideration is given to various aspects, including maximizing efficiency, lowering manufacturing cost, and increasing performance. With these goals in mind, one area relating to the preferred embodiments is the continuing trend of reducing the thickness of the transistor gate dielectrics. For example, in the past the gate dielectric layer thickness was on the order of 100 Angstroms, but more recently that thickness has reduced considerably with a more current goal being on the order of 20 Angstroms. Indeed, this goal will strive for even thinner gate dielectric layers in the foreseeable future. This goal reduces device size and facilitates improved device performance.
While the above demonstrates the desirability and trend toward thinner gate dielectrics, such an approach also provides a considerable drawback. Specifically, overlying the thin gate dielectric is a polycrystalline silicon (“polysilicon”) gate layer, and it is known in the art that polysilicon naturally includes a depletion region at the interface between the polysilicon gate and the gate dielectric. Typically, the depletion region manifests itself as providing the electrical equivalent of approximately a 3 Angstrom thick insulator and, as such, the region in effect provides an insulating effect rather than a conducting effect as would be present in the remainder of the polysilicon gate conductor. Using the preceding numeric example, therefore, for a 100 Angstrom thick gate dielectric, then the overlying effective 3 Angstrom thick polysilicon depletion region may be thought to effectively increase the overall insulation between the gate and the underlying transistor channel from 100 Angstroms to 103 Angstroms, that is, the effect of the depletion region affects the insulating thickness by three percent—as such, for previous thicker gate insulators the effect of the polysilicon depletion region may be considered to have a negligible impact on the gate dielectric. In contrast, however, for a 20 Angstrom thick gate dielectric, then the polysilicon gate conductor depletion region may be thought to increase the gate insulator to 23 Angstroms, thereby representing an increase on the order of 15 percent. This increased percentage significantly reduces the benefits otherwise provided by the thinner gate dielectric.
By way of further background, one approach in general to avoiding the depletion region phenomenon of polysilicon transistor gates is to use metal as an alternative material for the transistor gate since metal does not present a considerable depletion region, if any. Prior to the more recent use of polysilicon gates, metal gates were fairly common. The present inventors note, however, a previously identified drawback of such metal gates, which indeed led to the avoidance of such metals in contemporary devices. Specifically, each metal has a corresponding so-called work function, and in the transistor art each transistor also has a corresponding preferred value for a work function of the gate electrode. However, the desired work function value differs for different transistor types. For example, based on present day threshold voltage channel doping, a p-channel MOS transistor (“PMOS”) is optimized when the gate electrode has a work function on the order of 5 eV while an n-channel MOS transistor (“NMOS”) is optimized when the gate electrode has a work function on the order of 4 eV. The problem with previously-used metal gates arose with the development of CMOS circuits which, by definition, include both PMOS and NMOS transistors. Specifically, because a metal gate provides only a single work function, then it could not be selected to provide the two different desired work functions of the PMOS and NMOS devices. Instead, at best a metal could be selected to be between the desired work function of a PMOS and an NMOS transistor, which is sometimes referred to as the “midgap” between these devices (i.e., on the order of 4.5 eV for the preceding examples). This inability to match different work functions led to the use of polysilicon gates whereby the polysilicon gates of the NMOS devices could be doped in a first manner in view of the desired work function for NMOS transistors and the polysilicon gates of the PMOS devices could be doped in a second manner in view of the desired work function for PMOS transistors.
In view of the above, there arises a need to address the limitations and drawbacks of the prior art, as is achieved by the preferred embodiments described below.